What is FTUNSHADES?
FTUNSHADES is a hardware-accelerated fault injection platform for early assessment of the robustness of a circuit to SEE.
The system emulates a circuit running on an FPGA (Xilinx V5). Playing with the configuration bits, the runtime value of any selected register is flipped in a certain clock cycle, and its effects assessed.
The goal is to inspect a design, determine where protections should be inserted in the circuit architecture, and what the limits of those protections are.
What can it do for me?
FTUNSHADES campaigns are tailor made for injecting massive amounts of faults and automatically retrieve as much information as possible.
The targeted registers may be specified manually from every point of the hierarchy. Many options, modes and SEE models may be configured through the user friendly GUI.
Debugging allows the interruption of a campaign at arbitrary points to extract even more information from the system. Once interrupted, the system may be manually analyzed step by step.
A campaign in which the FPGA itself is the target device. Configuration bits are selected and flipped as would happen to registers during a campaign.
Fault detection is usually performed cycle by cycle. This condition is too much restrictive for systems like an embedded processor, where protections are inserted via software redundancies. An original technique called "smart table" has been implemented.
For fault diagnosis, a technique based on hash codes has been developed to analyse and compare the signatures of faults in a fault injection campaign with the real circuit in the accelerator beam.
After fault injection detects the most sensitive parts of a design, it is advisable to harden those. For this, we provide a VHDL package for fine-grain circuit hardening, the triple-logic package.
How do I make it work?
FTUNSHADES uses the standard Xilinx design flow. The user only needs to provide a list of I/O pins. The workflow is simple and the interface itself guides you step by step.
The only limits are:
- ISE 12.1 to ISE 14.7 have been tested.
- Designs have to fit in either
- a XC5VFX70T device (Universidad de Sevilla model) or...
- a XC5VLX50T device (European Space Agency model).
- Designs are limited to 512 I/Os (XC5VFX70T) or 411 I/Os (XC5VLX50T). Clock input does not count towards this maximum.
FTUNSHADES devices are able to extract the following information:
- Fault dictionary: injection schema (where, when and how) + effects of the fault.
- Fault classification by hierarchy, category (silent, damage and latent) or sistemic damage.
- Fault propagation analysis. Interactive analysis and internal details.
- AVF (Architectural Vulnerability Factor) of any complex digital design
- Dynamic sensitivity in Virtex-5 FPGAs to SEU in configuration bits.
Where can I use it?
FTUNSHADES is available on the cloud, free of charge, to public research institutions.
A proposal of research activity must be sent to the development team specifying the subject, mode of use, and time window needed. The development team will decide the access mode and credentials will be sent to the research activity responsible.
Note that few nodes are available and we can receive many requests.
All publications produced by that activity must mention the FTUNSHADES project, the University of Sevilla and European Space Agency in the Acknowledgements section.
FTUNSHADES development team (in alphabetical order)
- Miguel A. Aguirre
- Javier Barrientos
- Hipólito Guzmán-Miranda
- Fernando Márquez
- Fernando Muñoz
- Luis Sanz
Collaborators and historical actors
- Javier Nápoles
- Juan Manuel Mogollón
- Jon Tombs
- Rogelio Palomo
- Vicente Baena
- Patricio Rodríguez
- Antonio Torralba
- David Merodio (ESA)
- Francisco Tortosa (formerly @ESA)
- Agustín Fernández-León (ESA)
- Richard Jansen (ESA)
- Luca Sterpone (Pol. di Torino)
- Massimo Violante (Pol. di Torino)
- Universidad de Sevilla
- European Space Agency
- AICIA (Asociación de Investigación y Cooperación Industrial de Andalucía)
- European Commission with the VEGAS Project (Validation of European high capacity rad-hard FPGA and software tools)
- Ministerio de Ciencia e Innovación with the projects RENASER (ESP2007-65914-C03-03), RENASER+ (TEC2010-22095-C03-01) and RENASER3 (ESP2015-68245-C4-2-P)
- Junta de Andalucía with project EDELWEISS (P11-TIC-7095)
- CDTI (Centro para el Desarrollo Tecnológico Industrial) with project EMULASER (PNE-034/2006)
- Hipólito Guzmán-Miranda
- Fernando Muñoz Chavero
- Miguel A. Aguirre
- Escuela Superior de Ingenieros, Departamento de Ingeniería Electrónica. Camino de los descubrimientos s/n 41092 Sevilla (SPAIN)